module sc_hier_bench();

    reg             ctr_rst;
    wire    [2:0]   out;

    sc_hier U0 (.out(out),  .ctr_rst(ctr_rst));
    initial
    begin
        ctr_rst = 0;
        #100
        ctr_rst = 1;
        #200
        ctr_rst = 0;
        #200
        ctr_rst = 1;
        #100
        ctr_rst = 0;
        #300
        ctr_rst = 1;
        #100
        ctr_rst = 0;
        #400
        ctr_rst = 1;
        #200
        ctr_rst = 0;
        #500
        ctr_rst = 1;
        #400
        ctr_rst = 0;
        #1000
        ctr_rst = 1;
        #200
        ctr_rst = 0;
        #200 $finish;
    end

    always @(ctr_rst, out)
    begin
        #1;
        $display ("out = %b rst = %b", out, ctr_rst);
    end
endmodule

